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cy8c28243, cy8c 28403, cy8c28413 cy8c28433, cy8c 28445, cy8c28452 cy8c28513, cy8c 28533, cy8c28545 extended industrial psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-46339 rev. *f revised november 10, 2009 features varied resource options within one psoc device group powerful harvard architecture processor ? m8c processor speeds up to 12 mhz ? 8x8 multiply, 32-bit accumulate ? low power at high speed ? 4.75v to 5.25v operating voltage ? extended temperature range: -40c to +105c advanced reconfigurable peripherals (psoc blocks) ? up to 12 rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 9-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? multiple adc configurations ? dedicated sar adc, up to 192 ksps with sample and hold ? up to 4 synchronized or independent delta-sigma adcs for advanced applications ? up to 4 limited type e analog blocks provide: ? dual channel capacitive sensing capability ? comparators with programmable dac reference ? up to 10-bit single-slope adcs ? up to 12 digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? shift register, crc, and prs modules ? up to 3 full-duplex uarts ? up to 6 half-duplex uarts ? multiple variable data length spi ? masters or slaves ? connectable to all gpio ? complex peripherals by combining blocks precision, programmable clocking ? internal 4% 24 mh z main oscillator ? optional 32.768 khz crystal for precise on-chip clocks ? optional external oscillator, up to 24 mhz ? internal low speed, low power oscillator for watchdog and sleep functionality flexible on-chip memory ? 16k bytes flash program storage 100 erase/write cycles ? 1k bytes sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink, 10 ma drive on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? analog input on all gpio ? 30 ma analog outputs on gpio ? configurable interrupt on all gpio additional system resources ? up to 2 hardware i 2 c resources ? each resource implements slave, master, or multi-master modes ? operation between 0 and 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? flexible internal voltage references ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full featured in-circuit emulator, and programmer ? full speed emulation ? flexible and functional breakpoint structure ? 128k trace memory digital system sram 1k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array 2 macs switch mode pump internal voltage ref. digital clocks por and lvd system resets 4 type 2 decimators system resources analog system analog ref. analog input muxing 2 i 2 c blocks port 4 port 3 port 2 port 1 port 0 analog drivers system bus analog block array port 5 system block diagram [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 2 of 53 contents features ...............................................................................1 system block diagram .......................................................1 contents ..............................................................................2 psoc functional overview ................................................3 the psoc core .............................................................3 the digital system ........................................................3 the analog system .......................................................4 system resources ........................................................7 psoc device characteristics . .......................................7 getting started ....................................................................8 application notes ..........................................................8 development kits ..........................................................8 training .........................................................................8 cypros consultants ......................................................8 solutions library ............................................................8 technical support .........................................................8 development tools ............................................................8 psoc designer software subsyst ems ............ ..............8 in-circuit emulator .........................................................9 designing with psoc designer .........................................9 select components .......................................................9 configure components ............. .............. .............. ........9 organize and connect .............. .............. .............. ........9 generate, verify, and debug .........................................9 document conventions ...................................................10 acronyms used ...........................................................10 units of measure .........................................................10 numeric naming ..........................................................10 pinouts ..............................................................................11 20-pin part pinout ......................................................11 28-pin part pinout .......................................................12 44-pin part pinout ......................................................13 register reference ................. ........... ........... ........... .........14 register conventions ......................................................14 register mapping tables .................................................14 electrical specifications ..................................................27 absolute maximum ratings ...........................................28 operating temperature ...................................................28 dc electrical characteristics ..........................................29 dc chip level specifications ......................................29 dc general purpose i/o specifications ......................30 dc operational amplifier spec ifications ..... ........... .....30 dc type-e operational amplifier specifications .........31 dc low power comparator spec ifications .................33 dc analog output buffer spec ifications .....................33 dc analog reference specifications ..........................34 dc analog psoc block specif ications ........ ........... .....35 dc analog mux bus specifications .............................36 dc sar10 adc specifications ...................................36 dc por and lvd specifications ................................37 dc programming specifications ............ .............. .......37 ac electrical characteristics ..........................................38 ac chip level specifications ......................................38 ac general purpose i/o specifications ......................40 ac operational amplifier spec ifications ......................40 ac type-e operational amplifier specifications .........42 ac low power comparator sp ecifications . ........... .....42 ac analog mux bus specifications .............................42 ac digital block specifications ...................................42 ac analog output buffer specifications ......................43 ac sar10 adc specifications ...................................43 ac external clock specifications ................................44 ac programming specifications ..................................44 ac i2c specifications ..................................................44 packaging information .....................................................46 packaging dimensions ................................................46 thermal impedances .......................................................48 capacitance on crystal pins ..........................................48 solder reflow peak temperature ...................................48 development tool selection ..... .............. .............. ..........49 software ......................................................................49 development kits ........................................................49 evaluation tools ........ .............. ............... .............. .......49 device programmers ............... ....................................50 accessories (emulation and programming) ................50 ordering information ........................................................51 ordering code definitions ..... ......................................52 document history page ...................................................53 sales, solutions, and legal information ........................53 worldwide sales and design supp ort ............ .............53 products ......................................................................53 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 3 of 53 psoc functional overview the psoc family consists of many devices with on-chip controllers. these devices are designed to replace multiple traditional mcu based system components with one low cost single chip programmable component. a psoc device includes configurable analog bl ocks, digital blocks, and interco nnections. this architecture enables t he user to create customized peripheral configurations to match the requirements of each individual application. in addition, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the cy8c28xxx group of psoc devices described in this data sheet have multiple resource configuration options available. therefore, not every resource mentioned in this data sheet is available for each cy8c28xxx subgroup. the cy8c28x45 subgroup has a full feature set of all resources described. there are six more segmented subgroup s that allow designers to use a device with only the resources and functionality necessary for a specific application. see ta b l e 2 on page 7 to determine the resources available for each cy8c28xxx subgroup. the same information is also presented in more detail in the ordering infor- mation section. the architecture for this specif ic psoc device family, as shown in the system block diagram on page 1, consists of four main areas: psoc core, digital system, analog system, and system resources. the configurable g lobal bus system al lows all the device resources to be combined into a complete custom system. psoc cy8c28xxx family devices have up to six i/o ports that connect to the global digital and analog interconnects, providing access to up to 12 digital blocks an d up to 16 analog blocks. the psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable general purpose i/o (gpio). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture microcontroller. memory encompasses 16k bytes of flash for program storage, 1k bytes of sram for data storage. the psoc device incorpo- rates flexible internal clock generators, including a 24 mhz internal main oscillator (imo) ac curate to 2.5% over temperature and voltage. a low power 32 khz internal low speed oscillator (ilo) is provided for the sleep timer and watch dog timer (wdt). the 32.768 khz external crystal oscillator (eco) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz sy stem clock using a pll. psoc gpios provide connections to the cpu, and digital and analog resources. each pin?s drive mode may be selected from 8 options, which allows great flex ibility in external interfacing. every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. the digital system the digital system is composed of up to 12 configurable digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to create 8, 16, 24, and 32-bit peripherals, which are called user modules. the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. figure 1. digital system block diagram [1] digital peripheral configurations include: pwms (8 to 16 bit, one-shot and multi-shot capability) pwms with dead band/kill (8 to 16 bit) counters (8 to 32 bit) timers (8 to 32 bit) full-duplex 8-bit uarts (up to 3) with selectable parity half-duplex 8-bit uarts (up to 6) with selectable parity variable length spi slave and master ? up to 6 total slaves and masters (8-bit) ? supports 8 to 16 bit operation i 2 c slave, master, or multi-master (up to 2 available as system resources) irda (up to 3) pseudo random sequence generators (8 to 32 bit) cyclical redundancy checker/generator (16 bit) shift register (2 to 32 bit) digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 8 8 8 gie[7:0] gio[7:0] global digital interconnect port 4 port 3 port 2 port 1 port 0 port 5 goo[7:0] goe[7:0] row input configuration row 0 dbc00 dbc01 dcc02 dcc03 4 4 row output configuration row 1 dbc10 dbc11 dcc12 dcc13 row input configuration 4 4 row output configuration row 2 dbc20 dbc21 dcc22 dcc23 row input configuration 4 4 row output configuration note 1. cy8c28x52 devices do not have digital block row 2. they have two digital rows with eight total digital blocks. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 4 of 53 the analog system the analog system is composed of up to 16 configurable analog blocks, each containing an opamp ci rcuit that allows the creation of complex analog signal flows. some devices in this psoc family have an analog multiplex bus that can connect to every gpio pin. this bus can also connect to the analog system for analysis with comparators and analog-to-digital converters. it can be split into two sections for simultaneous dual-channel processing. some of the more common psoc analog functions (most available as user modules) are: analog-to-digital converters (6 to 14-bit resolution, up to 4, selectable as incremental or delta sigma) dedicated 10-bit sar adc with sample rates up to 192 ksps synchronized, simultaneous delta sigma adcs (up to 4) filters (2 to 8 pole band-pass, low-pass, and notch) amplifiers (up to 4, with selectable gain to 48x) instrumentation amplifiers (up to 2, with selectable gain to 93x) comparators (up to 6, with 16 selectable thresholds) dacs (up to 4, with 6 to 9-bit resolution) multiplying dacs (up to 4, with 6 to 9-bit resolution) high current output drivers (up to 4 with 30 ma drive) 1.3v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible figure 2. analog system block diagram for cy8c28x45 and cy8c28x52 devices acc00 acc01 block array array input configuration aci1[1:0] aci2[1:0] acc02 acc03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference ace00 ace01 ase10 ase11 analog mux bus all gpio aci4[1:0] aci5[1:0] [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 5 of 53 figure 3. analog system block diagram for cy8c28x43 devices figure 4. analog system block diagram for cy8c28x33 devices acc00 acc01 block array array input configuration aci1[1:0] aci2[1:0] acc02 acc03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference analog mux bus all gpio acc00 acc01 block array array input configuration aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference ace00 ace01 ase10 ase11 aci4[1:0] aci5[1:0] analog mux bus all gpio [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 6 of 53 figure 5. analog system block diagram for cy8c28x23 devices figure 6. analog system block diagram for cy8c28x13 devices acc00 acc01 block array array input configuration aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference block array array input configuration aci1[1:0] aci0[1:0] p0[6] p0[4] p0[2] p0[0] p0[7] p0[5] p0[3] p0[1] reference generators agndin refin bandgap refhi reflo agnd interface to digital system m8c interface (address bus, data bus, etc.) analog reference ace00 ace01 ase10 ase11 analog mux bus all gpio [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 7 of 53 system resources system resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. additional resources include a multiplier, multiple decimators, switch mode pump, low voltage detection, and power on reset. statements descri bing the merits of each system resource follow: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. multiply accumulate (mac) provid es fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. up to four decimators provide cu stom hardware filters for digital signal processing applications such as delta-sigma adcs and capsense capacitive sensor measurement. up to two i 2 c resources provide 0 to 400 khz communication over two wires. slave, master, and multi-master modes are all supported. i 2 c resources have hardware address detection capability. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates t he need for a system supervisor. an internal 1.3v reference provides an absolute reference for the analog system, includ ing adcs and dacs. psoc device characteristics there are other psoc device groups in addition to the one described in this data sheet. these other psoc device groups offer even more resource options. the following table lists the resources available for specific psoc device groups. the psoc device group covered by this data sheet is highlighted. the devices covered by this data sheet all have the same archi- tecture, specifications, and ra tings. however, the amount of some hardware resources varies from device to device within the group. the following table lists resources available for the specific device subgroups covered by this data sheet. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 12 4 4 12 2k 32k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12/4 [2] 1k 16k cy8c27x43 up to 44 2 8 12 4 4 12 256 bytes 16k cy8c24x94 64 1 4 48 2 2 6 1k 16k cy8c24x23 a up to 24 14 122 2 6 256 bytes 4k cy8c23x33 up to 1 4 12 2 2 4 256 bytes 8k cy8c21x34 up to 28 14 280 2 4 [3] 512 bytes 8k cy8c21x23 16 1 4 8 0 2 4 [3] 256 bytes 4k cy8c20x34 up to 28 0 0 28 0 0 3 [4] 512 bytes 8k table 2. cy8c28xxx device characteristics psoc part number capsense digital blocks regular analog blocks limited analog blocks hw i 2 c decimators digital i/o analog inputs analog outputs cy8c28x03 n 12 0 0 2 0 up to 24 up to 8 0 cy8c28x13 y 12 0 4 1 2 up to 40 up to 40 0 cy8c28x23 n 12 6 0 2 2 up to 44 up to 10 2 cy8c28x33 y 12 6 4 1 4 up to 40 up to 40 2 cy8c28x43 n 12 12 0 2 4 up to 44 up to 44 4 cy8c28x45 y 12 12 4 2 4 up to 44 up to 44 4 cy8c28x52 y 8 12 4 1 4 up to 24 up to 24 4 notes 2. has 12 regular analog blocks and four limited type-e analog blocks. 3. limited analog functionality . 4. two analog blocks and one capsense. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 8 of 53 getting started the quickest way to understand psoc silicon is to read this data sheet and then use the psoc designer integrated development environment (ide). this data sh eet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the psoc? programmable system-on-chip technical referenc e manual for cy8c28xxx psoc devices. for up-to-date ordering, packaging , and electrical specification information, see the latest psoc device data sheets on the web at www.cypress.com/psoc . application notes application notes are an excellent introduction to the wide variety of possible psoc designs. they are located here: www.cypress.com/psoc . select application notes under the documentation tab. development kits psoc development kits are available online from cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to www.cypress.com/cypros . solutions library visit our growing library of solution focused designs at www.cypress.com/solutions . here you can find various appli- cation designs that include firm ware and hardware design files that enable you to complete your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at www.cypress.com/support . if you cannot find an answer to your question, call technical support at 1-800-541-4736. development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide runs on windows xp or windows vista. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and built -in support for third-party assemblers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer software subsystems system-level view a drag-and-drop visual embedded system design environment based on psoc express. in the system level view you create a model of your system inputs, ou tputs, and communication inter- faces. you define when and how an output device changes state based upon any or all other system devices. based upon the design, psoc designer automatically selects one or more psoc on-chip controllers that match your system requirements. psoc designer generates all embedded code, then compiles and links it into a programming file for a specific psoc device. chip-level view the chip-level view is a more traditional integrated development environment (ide) based on psoc designer 4.4. choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modu les are adcs, dacs, amplifiers, and filters. configure the us er modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configuration allows for changing configurations at run time. hybrid designs you can begin in the system-level view, allow it to choose and configure your user modules, routing, and gener ate code, then switch to the chip-level view to gain complete control over on-chip resources. all views of the project share a common code editor, builder, and common debug, emulation, and programming tools. code generation tools psoc designer supports multiple third party c compilers and assemblers. the code generatio n tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow assembly code to merge seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the psoc device. 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cy8c28xxx document number: 001-46339 rev. *f page 9 of 53 debugger commands allow the designer to read and program and read and write data memory, read and write i/o registers, read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context- sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to fa qs and an online support forum to aid the designer in getting started. in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-se lectable functions. the psoc development process can be summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify, and debug select components both the system-level and chip-l evel views provide a library of prebuilt, pretested hardware peripheral components. in the system-level view, these com ponents are called ?drivers? and correspond to inputs (a thermistor, for example), outputs (a brushless dc fan, for example), communication interfaces (i 2 c-bus, for example), and the logic to control how they interact with one another (called valuators). in the chip-level view, the components are called ?user modules?. user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. configure components each of the components you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the psoc designer. these data sheets expl ain the internal operation of the component and provide performance specifications. each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. organize and connect you can build signal chains at the chip level by interconnecting user modules to each other and the i/o pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. in the system-level view, sele cting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (pga) to buffer the input from the potentiometer, an analog to digital converter (adc) to conver t the potentiometer?s output to a digital signal, and a pwm to control the fan. in the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the software for the system. both system-level and chip-level designs generate software based on your design. the chip-level design provides application programming interfaces (apis) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. the system-level design also generates a c ma in() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-va riable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. 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cy8c28xxx document number: 001-46339 rev. *f page 10 of 53 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 18 on page 27 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h? or ?b? are decimal. acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose i/o gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator i/o input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sar successive approximation register sc switched capacitor slimo slow imo smp switch mode pump sram static random access memory [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 11 of 53 pinouts this section describes, lists, and illustrates the cy8c28xxx psoc device pins and pinout configurations. the cy8c28xxx psoc devices are available in a variety of packages which are listed and illu strated in the following tables. eve ry port pin (labeled with a ?p?) is capable of digital i/o. howeve r, vss, vdd, smp, and xres are not capable of digital i/o. 20-pin part pinout table 3. 20-pin part pinout (ssop) pin no. type pin name description cy8c28243 20-pin psoc device digital analog 1 i/o i, m, s p0[7] analog column mux and sar adc input. [5] 2 i/o i/o, m, s p0[5] analog column mux and sar adc input. analog column output. [5, 6] 3 i/o i/o, m, s p0[3] analog column mux and sar adc input. analog column output. [5, 6] 4 i/o i, m, s p0[1] analog column mux and sar adc input. [5] 5 output smp switch mode pump (smp) connection to external components. 6 i/o m p1[7] i2c0 seri al clock (scl). 7 i/o m p1[5] i2c0 serial data (sda). 8 i/o m p1[3] 9 i/o m p1[1] crystal input (x talin), i2c0 serial clock (scl), issp-sclk [4] . 10 power vss ground connection. 11 i/o m p1[0] crystal output (xtalout), i2c0 serial data (sda), issp-sdata [4] . 12 i/o m p1[2] i2c1 serial data (sda). [7] 13 i/o m p1[4] optional external clock input (extclk). 14 i/o m p1[6] i2c1 seri al clock (scl). [7] 15 input xres active high external reset with internal pull down. 16 i/o i, m, s p0[0] analog column mux and sar adc input. [5] 17 i/o i/o, m, s p0[2] analog column mux and sar adc input. analog column output. [5, 8] 18 i/o i/o, m, s p0[4] analog column mux and sar adc input. analog column output. [5, 8] 19 i/o i, m, s p0[6] analog column mux and sar adc input. [5] 20 power vdd supply voltage. legend : a = analog, i = input, o = output, s = sar adc input, and m = analog mux bus input. ssop 2 1 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vdd p0[6], m, ai, s p0[4], m, aio, s p0[2], m, aio, s p0[0], m, ai, s xres p1[6], m, i2c1 scl p1[4], m, extclk p1[2], m, i2c1 sda p1[0], m, xtalout, i2c0 sda s, ai, m, p0[7] s, aio, m, p0[5] s, aio, m, p0[3] s, ai, m, p0[1] smp i2c0 scl, m, p1[7] i2c0 sda, m, p1[5] m, p1[3] i2c0 scl, xtalin, m, p1[1] vss notes 4. these are the issp pins, which are not high z at por (power on reset). see the psoc programmable system-on-chip technical reference manual for cy8c28xxx psoc devices for details. 5. cy8c28x52 and cy8c28x23 devices do not have a sar adc. therefore, this pin does not fu nction as a sar adc input for these dev ices. 6. cy8c28x13 and cy8c28x03 devices do not have any analog output buffers. therefore, th is pin does not function as an analog col umn output for these devices. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 12 of 53 28-pin part pinout table 4. 28-pin part pinout (ssop) pin no. type pin name description cy8c28413, cy8c28433, cy8c28445, and cy8c28452 28-pin psoc devices digital analog 1 i/o i, m, s p0[7] analog column mux and sar adc input. [5] 2 i/o i/o, m, s p0[5] analog column mux and sar adc input. analog column output. [5, 6] 3 i/o i/o, m, s p0[3] analog column mux and sar adc input. analog column output. [5, 6] 4 i/o i, m, s p0[1] analog column mux and sar adc input. [5] 5 i/o m p2[7] 6 i/o m p2[5] 7 i/o i, m p2[3] direct switched capacitor block input. [9] 8 i/o i, m p2[1] direct switched capacitor block input. [9] 9 output smp switch mode pump (smp) connection to external components. 10 i/o m p1[7] i2c0 serial clock (scl). 11 i/o m p1[5] i2c0 serial data (sda). 12 i/o m p1[3] 13 i/o m p1[1] crystal input (xtalin), i2c0 serial clock (scl), issp-sclk [4] . 14 power vss ground connection. 15 i/o m p1[0] crystal output (xtalout), i2c0 serial data (sda), issp-sdata [4] . 16 i/o m p1[2] i2c1 serial data (sda). [7] 17 i/o m p1[4] optional external clock input (extclk). 18 i/o m p1[6] i2c1 serial clock (scl). [7] 19 input xres active high external reset with internal pull down. 20 i/o i, m p2[0] direct switched capacitor block input. [10] 21 i/o i, m p2[2] direct switched capacitor block input. [10] 22 i/o m p2[4] external analog ground (agnd). 23 i/o m p2[6] external voltage reference (vref). 24 i/o i, m, s p0[0] analog column mux and sar adc input. [5] 25 i/o i/o, m, s p0[2] analog column mux and sar adc input. analog column output. [5, 8] 26 i/o i/o, m, s p0[4] analog column mux and sar adc input. analog column output. [5, 8] 27 i/o i, m, s p0[6] analog column mux and sar adc input. [5] 28 power vdd supply voltage. legend : a = analog, i = input, o = output, s = sar adc input, and m = analog mux bus input ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd p0[6], m, ai, s p0[4], m, aio, s p0[2], m, aio, s p0[0], m, ai, s p2[6], m, external vref p2[4], m, external agnd p2[2], m, ai p2[0], m, ai xres p1[6], m, i2c1 scl p1[4], m, extclk p1[2], m, i2c1 sda p1[0], m, xtalout, i2c0 sda s, ai, m, p0[7] s, aio, m, p0[5] s, aio, m, p0[3] s, ai, m, p0[1] m, p2[7] m, p2[5] ai, m, p2[3] ai, m, p2[1] smp i2c0 scl, m, p1[7] i2c0 sda, m, p1[5] m, p1[3] i2c0 scl, xtalin, m, p1[1] vss notes 7. cy8c28x52, cy8c28x13, and cy8c28x33 device s only have one i2c block. therefore, this gpio does not function as an i2c pin for these devices. 8. cy8c28x33, cy8c28x23, cy8c28x13, and cy8c28x 03 devices do not have an analog output buffer for this pin. therefore, this pin does not function as an analog column output for these devices. 9. this pin is not a direct switched capacitor blo ck analog input for cy8c28x03 and cy8c28x13 devices. 10. this pin is not a direct switched capacitor block analog input for cy8c28x03, cy8c28x13, cy8c28x23, and cy8c28x33 devices. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 13 of 53 44-pin part pinout table 5. 44-pin part pinout (tqfp) pin no. type pin name description cy8c28513, cy8c28533, and cy8c28545 44-pin psoc devices digital analog 1 i/o m p2[5] 2 i/o i, m p2[3] direct switched capacitor block input. [9] 3 i/o i, m p2[1] direct switched capacitor block input. [9] 4 i/o m p4[7] 5 i/o m p4[5] 6 i/o m p4[3] 7 i/o m p4[1] 8 output smp switch mode pump (smp) connection to external components. 9 i/o m p3[7] 10 i/o m p3[5] 11 i/o m p3[3] 12 i/o m p3[1] 13 i/o m p1[7] i2c0 serial clock (scl). 14 i/o m p1[5] i2c0 serial data (sda). 15 i/o m p1[3] 16 i/o m p1[1] crystal input (xtalin), i2c0 serial clock (scl), issp-sclk [4] . 17 output vss ground connection. 18 i/o m p1[0] crystal output (xtalout), i2c0 serial data (sda), issp-sdata [4] . 19 i/o m p1[2] i2c1 serial data (sda). [7] 20 i/o m p1[4] optional external clock input (extclk). 21 i/o m p1[6] i2c1 serial clock (scl). [7] 22 i/o m p3[0] i2c1 serial data (sda). [7] 23 i/o m p3[2] i2c1 serial clock (scl). [7] 24 i/o m p3[4] 25 i/o m p3[6] 26 input xres active high external reset with internal pull down. 27 i/o m p4[0] 28 i/o m p4[2] 29 i/o m p4[4] 30 i/o m p4[6] 31 i/o i, m p2[0] direct switched capacitor block input. [10] 32 i/o i, m p2[2] direct switched capacitor block input. [10] 33 i/o m p2[4] external analog ground (agnd). 34 i/o m p2[6] external voltage reference (vref). 35 i/o i, m, s p0[0] analog column mux and sar adc input. [5] 36 i/o i/o, m, s p0[2] analog column mux and sar adc input. analog column output. [5, 8] 37 i/o i/o, m, s p0[4] analog column mux and sar adc input. analog column output. [5, 8] 38 i/o i, m, s p0[6] analog column mux and sar adc input. [5] 39 power vdd supply voltage. 40 i/o i, m, s p0[7] analog column mux and sar adc input. [5] 41 i/o i/o, m, s p0[5] analog column mux and sar adc input. analog column output. [5, 6] 42 i/o i/o, m, s p0[3] analog column mux and sar adc input. analog column output. [5, 6] 43 i/o i, m, s p0[1] analog column mux and sar adc input. [5] 44 i/o p2[7] legend : a = analog, i = input, o = output, s = sar adc input, and m = analog mux bus input. tqfp 44 43 42 41 40 39 38 37 36 35 34 13 14 15 16 17 18 19 20 21 22 12 1 2 3 4 5 6 7 8 9 10 11 m, p2[5] ai, m, p2[3] ai, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] smp m, p3[7] m, p3[5] m, p3[3] m, p3[1] i2c0 scl, m, p1[7] i2c0 sda, m, p1[5] m, p1[3] i2c0 scl, xtalin, m, p1[1] vss i2c0 sda, xtalout, m, p1[0] i2c1 sda, m, p1[2] extclk, m, p1[4] i2c1 scl, m, p1[6] i2c1 sda, m, p3[0] p2[4], m, external agnd p2[2], m, ai p2[0], m, ai p4[6], m p4[4], m p4[2], m p4[0], m xres p3[6], m p3[4], m p3[2], m, i2c1 scl p2[7], m p0[1], m, ai, s p0[3], m, aio, s p0[5], m, aio, s p0[7], m, ai, s vdd p0[6], m, ai, s p0[4], m, aio, s p0[2], m, aio, s p0[0], m, ai, s p2[6], m, external vref 33 32 31 30 29 28 27 26 25 24 23 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 14 of 53 register reference this section lists the registers of the cy8c28xxx psoc de vices. for detailed register information, reference the psoc programmable system-on-chip technical reference manual for cy8c28xxx psoc devices. register conventions the register conventions specific to this section are listed in the following table. register mapping tables cy8c28xxx psoc devices have a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks. the xio bit in the flag register (cpu_f) determines which bank of registers cpu instructions access. when the xio bit is set the registers in bank 1 are accessed by cpu instructions. when the xio bit is cleared the registers in bank 0 are accessed by cpu instructions. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 15 of 53 table 6. cy8c28x03 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # 80 rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w 81 rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw 82 rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # 83 rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # 84 rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w 85 rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw 86 rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # 87 rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # 88 c8 prt2ie 09 rw dcc22dr1 49 w 89 c9 prt2gs 0a rw dcc22dr2 4a rw 8a ca prt2dm2 0b rw dcc22cr0 4b # 8b cb prt3dr 0c rw dcc23dr0 4c # 8c cc prt3ie 0d rw dcc23dr1 4d w 8d cd prt3gs 0e rw dcc23dr2 4e rw 8e ce prt3dm2 0f rw dcc23cr0 4f # 8f cf prt4dr 10 rw 50 90 cur_pp d0 rw prt4ie 11 rw 51 91 stk_pp d1 rw prt4gs 12 rw 52 92 d2 prt4dm2 13 rw 53 93 idx_pp d3 rw prt5dr 14 rw 54 94 mvr_pp d4 rw prt5ie 15 rw 55 95 mvw_pp d5 rw prt5gs 16 rw 56 96 i2c0_cfg d6 rw prt5dm2 17 rw 57 97 i2c0_scr d7 # 18 58 98 i2c0_dr d8 rw 19 59 99 i2c0_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f int_msk2 df rw dbc00dr0 20 # 60 a0 int_msk0 e0 rw dbc00dr1 21 w 61 a1 int_msk1 e1 rw dbc00dr2 22 rw 62 a2 int_vc e2 rc dbc00cr0 23 # 63 a3 res_wdt e3 w dbc01dr0 24 # 64 a4 i2c1_scr e4 # dbc01dr1 25 w 65 a5 i2c1_mscr e5 # dbc01dr2 26 rw 66 a6 e6 dbc01cr0 27 # i2c1_dr 67 rw a7 e7 dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # 70 rdi0ri b0 rw f0 dbc10dr1 31 w 71 rdi0syn b1 rw f1 dbc10dr2 32 rw 72 rdi0is b2 rw f2 dbc10cr0 33 # 73 rdi0lt0 b3 rw f3 dbc11dr0 34 # 74 rdi0lt1 b4 rw f4 dbc11dr1 35 w 75 rdi0ro0 b5 rw f5 dbc11dr2 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr0 37 # 77 rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # 78 rdi1ri b8 rw f8 dcc12dr1 39 w 79 rdi1syn b9 rw f9 dcc12dr2 3a rw 7a rdi1is ba rw fa dcc12cr0 3b # 7b rdi1lt0 bb rw fb dcc13dr0 3c # 7c rdi1lt1 bc rw fc dcc13dr1 3d w 7d rdi1ro0 bd rw fd dcc13dr2 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 16 of 53 table 7. cy8c28x03 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw 83 rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw 85 rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw 86 rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw 87 rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 c8 prt2dm1 09 rw dcc22in 49 rw 89 c9 prt2ic0 0a rw dcc22ou 4a rw 8a ca prt2ic1 0b rw dcc22cr1 4b rw 8b cb prt3dm0 0c rw dcc23fn 4c rw 8c cc prt3dm1 0d rw dcc23in 4d rw 8d cd prt3ic0 0e rw dcc23ou 4e rw 8e ce prt3ic1 0f rw dcc23cr1 4f rw 8f cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 91 gdi_e_in d1 rw prt4ic0 12 rw 52 92 gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 d4 prt5dm1 15 rw 55 95 d5 prt5ic0 16 rw 56 96 d6 prt5ic1 17 rw 57 97 d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw 60 gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw 61 gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw 62 gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw 63 gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw 64 rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw 65 rtc_m a5 rw e5 dbc01ou 26 rw 66 rtc_s a6 rw e6 dbc01cr1 27 rw 67 rtc_cr a7 rw e7 dcc02fn 28 rw 68 sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw 69 sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw 6a sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw i2c1_cfg 6b rw sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw ec dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw ed dcc03ou 2e rw tmp_dr2 6e rw i2c1_addr ae rw ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw 73 rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw 75 rdi0ro0 b5 rw f5 dbc11ou 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr1 37 rw 77 rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw 79 rdi1syn b9 rw f9 dcc12ou 3a rw 7a rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw 7b rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw 7d rdi1ro0 bd rw fd dcc13ou 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 17 of 53 table 8. cy8c28x13 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # 80 rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w 81 rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw 82 rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # 83 rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # 84 rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w 85 rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw 86 rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # 87 rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # 88 c8 prt2ie 09 rw dcc22dr1 49 w 89 c9 prt2gs 0a rw dcc22dr2 4a rw 8a ca prt2dm2 0b rw dcc22cr0 4b # 8b cb prt3dr 0c rw dcc23dr0 4c # 8c cc prt3ie 0d rw dcc23dr1 4d w 8d cd prt3gs 0e rw dcc23dr2 4e rw 8e ce prt3dm2 0f rw dcc23cr0 4f # 8f cf prt4dr 10 rw 50 90 cur_pp d0 rw prt4ie 11 rw 51 91 stk_pp d1 rw prt4gs 12 rw 52 92 d2 prt4dm2 13 rw 53 93 idx_pp d3 rw prt5dr 14 rw 54 94 mvr_pp d4 rw prt5ie 15 rw 55 95 mvw_pp d5 rw prt5gs 16 rw 56 96 i2c0_cfg d6 rw prt5dm2 17 rw 57 97 i2c0_scr d7 # 18 58 98 i2c0_dr d8 rw 19 59 99 i2c0_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f int_msk2 df rw dbc00dr0 20 # 60 dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw 62 dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # 63 dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # 64 a4 e4 dbc01dr1 25 w 65 a5 e5 dbc01dr2 26 rw 66 a6 dec_cr0* e6 rw dbc01cr0 27 # 67 a7 dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # 70 rdi0ri b0 rw f0 dbc10dr1 31 w 71 rdi0syn b1 rw f1 dbc10dr2 32 rw 72 rdi0is b2 rw f2 dbc10cr0 33 # 73 rdi0lt0 b3 rw f3 dbc11dr0 34 # 74 rdi0lt1 b4 rw f4 dbc11dr1 35 w 75 rdi0ro0 b5 rw f5 dbc11dr2 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr0 37 # 77 rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # 78 rdi1ri b8 rw f8 dcc12dr1 39 w 79 rdi1syn b9 rw f9 dcc12dr2 3a rw 7a rdi1is ba rw fa dcc12cr0 3b # 7b rdi1lt0 bb rw fb dcc13dr0 3c # 7c rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w 7d rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 18 of 53 table 9. cy8c28x13 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw ace_amd_cr1 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw ace_pwm_cr 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw ace_adc0_cr 86 rw rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw ace_adc1_cr 87 rw rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 c8 prt2dm1 09 rw dcc22in 49 rw ace_clk_cr0 89 rw c9 prt2ic0 0a rw dcc22ou 4a rw ace_clk_cr1 8a rw ca prt2ic1 0b rw dcc22cr1 4b rw ace_clk_cr3 8b rw cb prt3dm0 0c rw dcc23fn 4c rw 8c rw cc prt3dm1 0d rw dcc23in 4d rw ace01cr1 8d rw cd prt3ic0 0e rw dcc23ou 4e rw ace01cr2 8e rw ce prt3ic1 0f rw dcc23cr1 4f rw ase11cr0 8f rw cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 96 d6 prt5ic1 17 rw 57 97 d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c idac_cr1 dc rw 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw 60 gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw 61 gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw 62 gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw 63 gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw 64 rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw 65 rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw 66 rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw 67 rtc_cr a7 rw idac_cr2 e7 rw dcc02fn 28 rw 68 sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw 69 sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw 6b sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw ae ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw ace_amd_cr0 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rw rdi0lt1 b4 rw f4 dbc11in 35 rw ace_amx_in 75 rw rdi0ro0 b5 rw f5 dbc11ou 36 rw ace_cmp_cr0 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace_cmp_cr1 77 rw rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw ace_cmp_gi_en 79 rw rdi1syn b9 rw f9 dcc12ou 3a rw ace_alt_cr0 7a rw rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw ace_abf_cr0 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw ace0_cr1 7d rw rdi1ro0 bd rw idac_cr0 fd rw dcc13ou 3e rw ace0_cr2 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw ace0_cr3 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 19 of 53 table 10. cy8c28x33 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # asd11cr3 87 rw rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # 88 c8 prt2ie 09 rw dcc22dr1 49 w 89 c9 prt2gs 0a rw dcc22dr2 4a rw 8a ca prt2dm2 0b rw dcc22cr0 4b # 8b cb prt3dr 0c rw dcc23dr0 4c # 8c cc prt3ie 0d rw dcc23dr1 4d w 8d cd prt3gs 0e rw dcc23dr2 4e rw 8e ce prt3dm2 0f rw dcc23cr0 4f # 8f cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 98 i2c0_dr d8 rw 19 59 99 i2c0_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # dec2_dh a4 rc e4 dbc01dr1 25 w asy_cr 65 # dec2_dl a5 rc e5 dbc01dr2 26 rw cmp_cr1 66 rw dec3_dh a6 rc dec_cr0* e6 rw dbc01cr0 27 # 67 dec3_dl a7 rc dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # 78 rdi1ri b8 rw f8 dcc12dr1 39 w 79 rdi1syn b9 rw f9 dcc12dr2 3a rw 7a rdi1is ba rw fa dcc12cr0 3b # 7b rdi1lt0 bb rw fb dcc13dr0 3c # 7c rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w 7d rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 20 of 53 table 11. cy8c28x33 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw ace_amd_cr1 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw ace_pwm_cr 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw ace_adc0_cr 86 rw rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw ace_adc1_cr 87 rw rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 rw c8 prt2dm1 09 rw dcc22in 49 rw ace_clk_cr0 89 rw c9 prt2ic0 0a rw dcc22ou 4a rw ace_clk_cr1 8a rw ca prt2ic1 0b rw dcc22cr1 4b rw ace_clk_cr3 8b rw cb prt3dm0 0c rw dcc23fn 4c rw 8c cc prt3dm1 0d rw dcc23in 4d rw ace01cr1 8d rw cd prt3ic0 0e rw dcc23ou 4e rw ace01cr2 8e rw ce prt3ic1 0f rw dcc23cr1 4f rw ase11cr0 8f rw cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 dec_cr4 96 rw dec2_cr d6 rw prt5ic1 17 rw 57 97 dec3_cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 dec2_cr0 99 rw mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c idac_cr1 dc rw 1d 5d dec3_cr0 9d rw osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw 65 rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw idac_cr2 e7 rw dcc02fn 28 rw 68 sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw 6b sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw ae ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw ace_amd_cr0 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw ace_amx_in 75 rw rdi0ro0 b5 rw f5 dbc11ou 36 rw ace_cmp_cr0 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace_cmp_cr1 77 rw rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw ace_cmp_gi_en 79 rw rdi1syn b9 rw f9 dcc12ou 3a rw ace_alt_cr0 7a rw rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw ace_abf_cr0 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw ace0_cr1 7d rw rdi1ro0 bd rw idac_cr0 fd rw dcc13ou 3e rw ace0_cr2 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw ace0_cr3 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 21 of 53 table 12. cy8c28x43 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # asd11cr3 87 rw rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # asc12cr0 88 rw c8 prt2ie 09 rw dcc22dr1 49 w asc12cr1 89 rw c9 prt2gs 0a rw dcc22dr2 4a rw asc12cr2 8a rw ca prt2dm2 0b rw dcc22cr0 4b # asc12cr3 8b rw cb prt3dr 0c rw dcc23dr0 4c # asd13cr0 8c rw cc prt3ie 0d rw dcc23dr1 4d w asd13cr1 8d rw cd prt3gs 0e rw dcc23dr2 4e rw asd13cr2 8e rw ce prt3dm2 0f rw dcc23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 asd22cr0 98 rw i2c0_dr d8 rw 19 59 asd22cr1 99 rw i2c0_mscr d9 # 1a 5a asd22cr2 9a rw int_clr0 da rw 1b 5b asd22cr3 9b rw int_clr1 db rw 1c 5c asc23cr0 9c rw int_clr2 dc rw 1d 5d asc23cr1 9d rw int_clr3 dd rw 1e 5e asc23cr2 9e rw int_msk3 de rw 1f 5f asc23cr3 9f rw int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # dec2_dh a4 rc i2c1_scr e4 # dbc01dr1 25 w asy_cr 65 # dec2_dl a5 rc i2c1_mscr e5 # dbc01dr2 26 rw cmp_cr1 66 rw dec3_dh a6 rc dec_cr0* e6 rw dbc01cr0 27 # i2c1_dr 67 rw dec3_dl a7 rc dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcc12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcc12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcc12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcc13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcc13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcc13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # acb03cr2 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 22 of 53 table 13. cy8c28x43 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw 83 rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw 85 rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw 86 rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw 87 rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 c8 prt2dm1 09 rw dcc22in 49 rw 89 c9 prt2ic0 0a rw dcc22ou 4a rw 8a ca prt2ic1 0b rw dcc22cr1 4b rw 8b cb prt3dm0 0c rw dcc23fn 4c rw 8c cc prt3dm1 0d rw dcc23in 4d rw 8d cd prt3ic0 0e rw dcc23ou 4e rw 8e ce prt3ic1 0f rw dcc23cr1 4f rw 8f cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 dec_cr4 96 rw dec2_cr d6 rw prt5ic1 17 rw 57 97 dec3_cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 dec2_cr0 99 rw mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c dc 1d 5d dec3_cr0 9d rw osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw e5 dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw e6 dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw e7 dcc02fn 28 rw alt_cr1 68 rw sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw i2c1_cfg 6b rw sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw i2c1_addr ae rw ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw 73 rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw 75 rdi0ro0 b5 rw f5 dbc11ou 36 rw 76 rdi0ro1 b6 rw f6 dbc11cr1 37 rw 77 rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw 79 rdi1syn b9 rw f9 dcc12ou 3a rw 7a rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw 7b rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw 7d rdi1ro0 bd rw fd dcc13ou 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 23 of 53 table 14. cy8c28x45 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbc20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbc20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbc20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbc20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbc21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbc21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbc21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbc21cr0 47 # asd11cr3 87 rw rdi2dsm c7 rw prt2dr 08 rw dcc22dr0 48 # asc12cr0 88 rw c8 prt2ie 09 rw dcc22dr1 49 w asc12cr1 89 rw c9 prt2gs 0a rw dcc22dr2 4a rw asc12cr2 8a rw ca prt2dm2 0b rw dcc22cr0 4b # asc12cr3 8b rw cb prt3dr 0c rw dcc23dr0 4c # asd13cr0 8c rw cc prt3ie 0d rw dcc23dr1 4d w asd13cr1 8d rw cd prt3gs 0e rw dcc23dr2 4e rw asd13cr2 8e rw ce prt3dm2 0f rw dcc23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 asd22cr0 98 rw i2c0_dr d8 rw 19 59 asd22cr1 99 rw i2c0_mscr d9 # 1a 5a asd22cr2 9a rw int_clr0 da rw 1b 5b asd22cr3 9b rw int_clr1 db rw 1c 5c asc23cr0 9c rw int_clr2 dc rw 1d 5d asc23cr1 9d rw int_clr3 dd rw 1e 5e asc23cr2 9e rw int_msk3 de rw 1f 5f asc23cr3 9f rw int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # dec2_dh a4 rc i2c1_scr e4 # dbc01dr1 25 w asy_cr 65 # dec2_dl a5 rc i2c1_mscr e5 # dbc01dr2 26 rw cmp_cr1 66 rw dec3_dh a6 rc dec_cr0* e6 rw dbc01cr0 27 # i2c1_dr 67 rw dec3_dl a7 rc dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw sadc_dh 6a rw mul1_dh aa r mul0_dh ea r dcc02cr0 2b # sadc_dl 6b rw mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcc12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcc12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcc12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcc13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # acb03cr2 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 24 of 53 table 15. cy8c28x45 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbc20fn 40 rw 80 rw rdi2ri c0 rw prt0dm1 01 rw dbc20in 41 rw sadc_tscmpl 81 rw rdi2syn c1 rw prt0ic0 02 rw dbc20ou 42 rw sadc_tscmph 82 rw rdi2is c2 rw prt0ic1 03 rw dbc20cr1 43 rw ace_amd_cr1 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbc21fn 44 rw 84 rw rdi2lt1 c4 rw prt1dm1 05 rw dbc21in 45 rw ace_pwm_cr 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbc21ou 46 rw ace_adc0_cr 86 rw rdi2ro1 c6 rw prt1ic1 07 rw dbc21cr1 47 rw ace_adc1_cr 87 rw rdi2dsm c7 rw prt2dm0 08 rw dcc22fn 48 rw 88 rw c8 prt2dm1 09 rw dcc22in 49 rw ace_clk_cr0 89 rw c9 prt2ic0 0a rw dcc22ou 4a rw ace_clk_cr1 8a rw ca prt2ic1 0b rw dcc22cr1 4b rw ace_clk_cr3 8b rw cb prt3dm0 0c rw dcc23fn 4c rw 8c rw cc prt3dm1 0d rw dcc23in 4d rw ace01cr1 8d rw cd prt3ic0 0e rw dcc23ou 4e rw ace01cr2 8e rw ce prt3ic1 0f rw dcc23cr1 4f rw ase11cr0 8f rw cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 dec_cr4 96 rw dec2_cr d6 rw prt5ic1 17 rw 57 97 dec3_cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 dec2_cr0 99 rw mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c idac_cr1 dc rw 1d 5d dec3_cr0 9d rw osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw idac_cr2 e7 rw dcc02fn 28 rw alt_cr1 68 rw sadc_cr0 a8 rw imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dcc02cr1 2b rw i2c1_cfg 6b rw sadc_cr3 ab rw eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw i2c1_addr ae rw ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw sadc_tscr0 71 rw rdi0syn b1 rw f1 dbc10ou 32 rw sadc_tscr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw ace_amd_cr0 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw ace_amx_in 75 rw rdi0ro0 b5 rw f5 dbc11ou 36 rw ace_cmp_cr0 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace_cmp_cr1 77 rw rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw ace_cmp_gi_en 79 rw rdi1syn b9 rw f9 dcc12ou 3a rw ace_alt_cr0 7a rw rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw ace_abf_cr0 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw ace0_cr1 7d rw rdi1ro0 bd rw idac_cr0 fd rw dcc13ou 3e rw ace0_cr2 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw ace0_cr3 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 25 of 53 table 16. cy8c28x52 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 asc10cr0 80 rw c0 prt0ie 01 rw 41 asc10cr1 81 rw c1 prt0gs 02 rw 42 asc10cr2 82 rw c2 prt0dm2 03 rw 43 asc10cr3 83 rw c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 asc12cr0 88 rw c8 prt2ie 09 rw 49 asc12cr1 89 rw c9 prt2gs 0a rw 4a asc12cr2 8a rw ca prt2dm2 0b rw 4b asc12cr3 8b rw cb prt3dr 0c rw 4c asd13cr0 8c rw cc prt3ie 0d rw 4d asd13cr1 8d rw cd prt3gs 0e rw 4e asd13cr2 8e rw ce prt3dm2 0f rw 4f asd13cr3 8f rw cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c0_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c0_scr d7 # 18 58 asd22cr0 98 rw i2c0_dr d8 rw 19 59 asd22cr1 99 rw i2c0_mscr d9 # 1a 5a asd22cr2 9a rw int_clr0 da rw 1b 5b asd22cr3 9b rw int_clr1 db rw 1c 5c asc23cr0 9c rw int_clr2 dc rw 1d 5d asc23cr1 9d rw int_clr3 dd rw 1e 5e asc23cr2 9e rw int_msk3 de rw 1f 5f asc23cr3 9f rw int_msk2 df rw dbc00dr0 20 # amx_in 60 rw dec0_dh a0 rc int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw dec0_dl a1 rc int_msk1 e1 rw dbc00dr2 22 rw clk_cr3 62 rw dec1_dh a2 rc int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw dec1_dl a3 rc res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # dec2_dh a4 rc e4 dbc01dr1 25 w asy_cr 65 # dec2_dl a5 rc e5 dbc01dr2 26 rw cmp_cr1 66 rw dec3_dh a6 rc dec_cr0* e6 rw dbc01cr0 27 # 67 dec3_dl a7 rc dec_cr1* e7 rw dcc02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcc02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcc02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcc02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcc03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbc10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbc10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbc10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbc11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbc11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # acb01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcc12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcc12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcc12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcc13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # acb03cr2 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 26 of 53 table 17. cy8c28x52 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 80 c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 ace_amd_cr1 83 rw c3 prt1dm0 04 rw 44 84 c4 prt1dm1 05 rw 45 ace_pwm_cr 85 rw c5 prt1ic0 06 rw 46 ace_adc0_cr 86 rw c6 prt1ic1 07 rw 47 ace_adc1_cr 87 rw c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 ace_clk_cr0 89 rw c9 prt2ic0 0a rw 4a ace_clk_cr1 8a rw ca prt2ic1 0b rw 4b ace_clk_cr3 8b rw cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d ace01cr1 8d rw cd prt3ic0 0e rw 4e ace01cr2 8e rw ce prt3ic1 0f rw 4f ase11cr0 8f rw cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 dec0_cr0 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 dec_cr3 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 93 gdi_e_ou d3 rw prt5dm0 14 rw 54 94 dec0_cr d4 rw prt5dm1 15 rw 55 dec1_cr0 95 rw dec1_cr d5 rw prt5ic0 16 rw 56 dec_cr4 96 rw dec2_cr d6 rw prt5ic1 17 rw 57 97 dec3_cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 dec2_cr0 99 rw mux_cr1 d9 rw 1a 5a dec_cr5 9a rw mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c idac_cr1 dc rw 1d 5d dec3_cr0 9d rw osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 rw dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw idac_cr2 e7 rw dcc02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 rw dcc02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 rw dcc02ou 2a rw amux_cfg1 6a rw aa bdg_tr ea rw dcc02cr1 2b rw 6b ab eco_tr eb rw dcc03fn 2c rw tmp_dr0 6c rw ac mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_addr ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw ae ee dcc03cr1 2f rw tmp_dr3 6f rw amux_clk af rw ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw 71 rdi0syn b1 rw f1 dbc10ou 32 rw 72 rdi0is b2 rw f2 dbc10cr1 33 rw ace_amd_cr0 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw ace_amx_in 75 rw rdi0ro0 b5 rw f5 dbc11ou 36 rw ace_cmp_cr0 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace_cmp_cr1 77 rw rdiodsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw ace_cmp_gi_en 79 rw rdi1syn b9 rw f9 dcc12ou 3a rw ace_alt_cr0 7a rw rdi1is ba rw fls_pr1 fa rw dcc12cr1 3b rw ace_abf_cr0 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw ace0_cr1 7d rw rdi1ro0 bd rw idac_cr0 fd rw dcc13ou 3e rw ace0_cr2 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr1 3f rw ace0_cr3 7f rw rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. *address has a dual purpose, see ?mapping exceptions? on page 251 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 27 of 53 electrical specifications this section presents the dc and ac electric al specifications of the cy8c28xxx psoc devi ces. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -40 o c t a 105 o c and t j 120 o c, except where noted. figure 7. voltage versus cpu frequency the following table lists the units of measure that are used in this section. table 18. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond ksps kilo-samples per second v microvolts sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage valid operating region [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 28 of 53 absolute maximum ratings operating temperature table 19. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 +25 +105 o c higher storage temperatures reduce data retention time. recommended storage temperature is +25c 25c. storage temperatures above 65 o c degrade reliability. maximum combined storage and operational time at +105c is 7000 hours. t a ambient temperature with power applied -40 ? +105 o c vdd supply voltage on vdd relative to vss -0.5 ? +5.5 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +25 ma i maio maximum current into any port pin configured as analog driver -50 ? +50 ma esd static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 20. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +105 o c t j junction temperature -40 ? +120 o c the temperature rise from ambient to junction is package specific. see thermal impedances on page 48. the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 29 of 53 dc electrical characteristics dc chip level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 21. dc chip level specifications symbol description min typ max units notes vdd supply voltage 4.75 ? 5.25 v i dd supply current ? 8 14 ma conditions are vdd = 5.25v, -40 o c t a 105 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. i ddp supply current when imo = 6 mhz using slimo mode ? 3.5 4 ma conditions are vdd = 5.0v, t a = 25 c, cpu = 0.75 mhz, sysclk doubler disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [11] ? 2.35 10 a conditions are with internal slow speed oscillator, vdd = 5.25v, -40 o c t a 55 o c. analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt. [11] ? 6.69 25 a conditions are with internal slow speed oscillator, vdd = 5.25v, 55 o c < t a 105 o c. analog power = off. i sbxtl sleep (mode) current with por, lvd, sleep timer, and wdt. [11] ? 7 16 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 5.25v, -40 o c t a 55 o c. analog power = off. i sbxtlh sleep (mode) current with por, lvd, sleep timer, and wdt. [11] ? 7 26 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 5.25v, 55 o c < t a 105 o c. analog power = off. i sbrtc current consumed by rtc during sleep ? 0.5 1 a extra current consumed by the rtc during sleep. this number is typical at 25 c and 5v. v ref reference voltage (bandgap) 1.28 1.3 1.32 v trimmed for appropriate vdd. i sxres supply current with xres asserted 5v ? 0.65 3 ma max is peak current after xres; typical value is the steady state current value. t a =25 c . ? 0.4 1.5 ma note 11. standby (sleep) current includes all function s (por, lvd, wdt, sleep timer) needed for reliable system operation. this should be compared with devices that have similar functions enabled. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 30 of 53 dc general purpose i/o specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. dc operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. the operational amplifiers covered by these specifications are components of both the analog continuous time psoc blocks and the analog switched cap psoc blocks. the guaranteed specifications are measured in the analog continuous time psoc block. table 22. dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level 3.5 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined iol budget. i oh high level source current 10 ? ? ma v oh = vdd-1.0v, see the limitations of the total current in the note for v oh. i ol low level sink current 25 ? ? ma v ol = 0.75v, see the limitations of the total current in the note for v ol. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.2 ? v vdd = 4.75 to 5.25. v h input hysteresis ? 110 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c. table 23. dc operational amplifier specifications symbol description min typ max units notes v osoact input offset voltage ct block (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.6 1.3 1.2 8 8 8 mv mv mv v osoa input offset voltage sc and agnd opamps (absolute value) ? 1 6 mv applies to high and low opamp bias. tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 10 pf package and pin dependent. temp = 25 o c. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 31 of 53 dc type-e operational amplifier specifications the following tables list the guaranteed maximum and minimum sp ecifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. the operational amplifiers covered by these specifications are components of the limited type e analog psoc blocks. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? vdd vdd - 0.5 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? cmrr oa common mode rejection ratio power = low power = medium power = high 60 60 60 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 50 db. g oloa open loop gain power = low power = medium power = high 60 60 80 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low power = medium power = high vdd - 0.2 vdd - 0.2 vdd - 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low power = medium power = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 200 400 700 1400 2400 4600 300 600 1100 2100 4000 8000 a a a a a a psrr oa supply voltage rejection ratio 60 ? ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd. table 24. dc type-e operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 17 mv for 0.2v < vin < vdd - 1.2v. ? 2.5 25 mv for vin = 0 to 0.2v and vin > vdd - 1.2v. tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa [12] input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0.0 ? vdd - 1 v i soa amplifier supply current ? 10 35 a table 23. dc operational amplifier specifications (continued) symbol description min typ max units notes [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 32 of 53 note 12. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1-7 for the lowest leakage of 200 na . [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 33 of 53 dc low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. dc analog output buffer specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 25. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v v oslpc lpc voltage offset ? 2.5 30 mv i slpc lpc supply current ? 10 40 a table 26. dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 18 mv tcv osob input offset voltage drift ? +6 20 v/c v cmob common-mode input voltage range .5 ? vdd - 1.0 v r outob output resistance ? 1 ? w v ohighob high output voltage swing (load = 32 ohms to vdd/2) .5 x vdd + 1.3 ? ? v v olowob low output voltage swing (load = 32 ohms to vdd/2) ? ? .5 x vdd - 1.3 v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 50 64 ? db (0.5 x vdd - 1.0) . vout . (0.5 x vdd + 0.9). [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 34 of 53 dc analog reference specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. the guaranteed specifications are measured through the analog continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time pso c block. the power levels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. note 13. agnd tolerance includes the offsets of the local buffer in the psoc block. table 27. dc analog reference specifications for high power symbol description min typ max units v bg5 bandgap voltage reference 5v 1.28 1.30 1.32 v ? agnd = vdd/2 [13] vdd/2 - 0.021 vdd/2 - 0.001 vdd/2 + 0.019 v ? agnd = 2 x bandgap [13] 2.527 2.593 2.659 v ? agnd = p2[4] (p2[4] = vdd/2) [13] p2[4] - 0.015 p2[4] - 0.002 p2[4] + 0.011 v ? agnd = bandgap [13] 1.28 1.31 1.34 v ? agnd = 1.6 x bandgap [13] 2.034 2.084 2.134 v ? agnd block to block variation (agnd = vdd/2) [13] -34 0.000 34 v ? refhi = vdd/2 + bandgap vdd/2 + 1.91 vdd/2 + 1.273 vdd/2 + 1.355 v ? refhi = 3 x bandgap 3.761 3.874 3.987 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) p2[6] + 2.478 p2[6] + 2.567 p2[6] + 2.722 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + 1.195 p2[4] + 1.273 p2[4] + 1.405 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.067 p2[4] + p2[6] + 0.028 p2[4] + p2[6] + 0.011 v ? refhi = 2 x bandgap 2.522 2.587 2.652 v ? refhi = 3.2 x bandgap 4.013 4.134 4.255 v ? reflo = vdd/2 ? bandgap vdd/2 - 1.371 vdd/2 - 1.310 vdd/2 - 1.249 v ? reflo = bandgap 1.247 1.311 1.375 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2.513 - p2[6] 2.586 - p2[6] 2.687 - p2[6] v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - 1.352 p2[4] - p2[6] - 0.008 p2[4] - 1.232 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.028 p2[4] - p2[6] - 0.014 p2[4] - p2[6] - 0.056 v table 28. dc analog reference specifications for medium power symbol description min typ max units v bg5 bandgap voltage reference 5v 1.28 1.30 1.32 v ? agnd = vdd/2 [13] vdd/2 - 0.021 vdd/2 -0.001 vdd/2 + 0.019 v ? agnd = 2 x bandgap [13] 2.534 2.596 2.658 v ? agnd = p2[4] (p2[4] = vdd/2) [13] p2[4] - 0.015 p2[4] -0.002 p2[4] + 0.011 v ? agnd = bandgap [13] 1.279 1.309 1.339 v ? agnd = 1.6 x bandgap [13] 2.035 2.085 2.135 v ? agnd block to block variation (agnd = vdd/2) [13] -34 0 34 v ? refhi = vdd/2 + bandgap vdd/2 + 1.196 vdd/2 +1.278 vdd/2 + 1.360 v ? refhi = 3 x bandgap 3.772 3.883 3.994 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) p2[6] + 2.492 p2[6] + 2.577 p2[6] + 2.708 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + 1.200 p2[4] + 1.278 p2[4] + 1.400 v [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 35 of 53 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.058 p2[4] + p2[6] -0.022 p2[4] + p2[6] + 0.014 v ? refhi = 2 x bandgap 2.523 2.589 2.655 v ? refhi = 3.2 x bandgap 4.02 4.141 4.262 v ? reflo = vdd/2 ? bandgap vdd/2 - 1.367 vdd/2 -1.306 vdd/2 - 1.245 v ? reflo = bandgap 1.243 1.31 1.377 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2.516 - p2[6] 2.588 - p2[6] 2.684 - p2[6] v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - 1.359 p2[4] - p2[6] - 0.004 p2[4] - 1.233 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.033 p2[4] - p2[6] - 0.008 p2[4] - p2[6] + 0.049 v table 28. dc analog reference specifications for medium power (continued) symbol description min typ max units table 29. dc analog reference specifications for low power symbol description min typ max units v bg5 bandgap voltage reference 5v 1.28 1.30 1.32 v ? agnd = vdd/2 [13] vdd/2 - 0.021 vdd/2 -0.001 vdd/2 + 0.019 v ? agnd = 2 x bandgap [13] 2.534 2.597 2.66 v ? agnd = p2[4] (p2[4] = vdd/2) [13] p2[4] - 0.015 p2[4] -0.002 p2[4] + 0.011 v ? agnd = bandgap [13] 1.279 1.309 1.339 v ? agnd = 1.6 x bandgap [13] 2.036 2.086 2.136 v ? agnd block to block variation (agnd = vdd/2) [13] -34 0 34 v ? refhi = vdd/2 + bandgap vdd/2 + 1.196 vdd/2 +1.278 vdd/2 + 1.360 v ? refhi = 3 x bandgap 3.773 3.886 3.999 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) p2[6] + 2.494 p2[6] + 2.579 p2[6] + 2.706 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + 1.201 p2[4] + 1.280 p2[4] + 1.399 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.055 p2[4] + p2[6] - 0.020 p2[4] + p2[6] + 0.015 v ? refhi = 2 x bandgap 2.525 2.59 2.655 v ? refhi = 3.2 x bandgap 4.022 4.143 4.264 v ? reflo = vdd/2 ? bandgap vdd/2 - 1.367 vdd/2 -1.304 vdd/2 - 1.241 v ? reflo = bandgap 1.243 1.31 1.377 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2.514 - p2[6] 2.588 - p2[6] 2.686 - p2[6] v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - 1.360 p2[4] - p2[6] - 0.003 p2[4] - 1.234 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.031 p2[4] - p2[6] - 0.007 p2[4] - p2[6] + 0.045 v table 30. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.24 ? k c sc capacitor unit value (switch cap) ? 80 ? ff [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 36 of 53 dc analog mux bus specifications the following table lists the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. dc sar10 adc specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 31. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 w vdd 3.0v r vss resistance of initialization switch to vss ? ? 800 w table 32. dc sar10 adc specifications symbol description min typ max units notes inl sar10 integral nonlinearity for vref 3 -2.5 - 2.5 lsb 10-bit resolution integral nonlinearity for vref < 3 -5 5 lsb 10-bit resolution dnl sar10 differential nonlinearity for vref 3 -1.5 - 1.5 lsb 10-bit resolution differential nonlinearity for vref < 3 -4 4 lsb 10-bit resolution i sar10 active current consumption 0.08 0.5 0.497 ma i vrefsar10 input current into p2[5] when configured as the sar10 adc's vref input. - - 0.5 ma the internal voltage reference buffer is disabled in this configu- ration. v vrefsar10 input reference voltage at p2[5] when configured as the sar10 adc's external voltage reference. 3.0 - 4.95 v when vref is buffered inside the sar10 adc, the voltage level at p2[5] (when configured as the external reference voltage) must always be at least 300 mv less than the chip supply voltage level on the vdd pin. (v vrefsar10 < (vdd - 300 mv) ). v ossar10 offset voltage 5 7.7 10 mv sar imp sar input impedence - 1.64 - m frequency dependant = 1/ fs c. 142.9 khz (maximum) and cin = 4.28 pf (typical) table 33. dc idac specifications symbol description min typ max units notes idac_dnl differential nonlinearity -5.0 2.0 5.0 lsb valid for all 3 current ranges idac_inl integral nonlinearity -5.0 2.0 5.0 lsb valid for all 3 current ranges idac_gain gain per bit - range 1 (91 a) 282 357 452 na measured at full scale gain per bit - range 2 (318 a) 985 1250 1533 na gain per bit - range 3 (637 a) 1959 2500 3057 na idacoffset offset at code 0 vs lsb ideal - range 1 (91 a) 2.0% 20% % measured as a % of lsb (current @ code 0)/(lsb ideal current) offset at code 0 vs lsb ideal - range 2 (318 a) 1.0% 10% % offset at code 0 vs lsb ideal - range 3 (637 a) 1.0% 10% % [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 37 of 53 dc por and lvd specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. see the psoc programmable system-on-chip technical reference manual for cy8c28xxx psoc devices, for more information on the vlt_cr register. dc programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 34. dc por and lvd specifications symbol description min typ max units notes v ppor1r v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0] = 01b porlev[1:0] = 10b ?4.39 4.55 4.49 4.65 v v v ppor1 v ppor2 vdd value for ppor trip (negative ramp) porlev[1:0] = 01b porlev[1:0] = 10b ?4.39 4.55 4.49 4.64 v v v ph1 v ph2 ppor hysteresis porlev[1:0] = 01b porlev[1:0] = 10b ? ? 0 0 ? ? mv mv v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 110b vm[2:0] = 111b 4.62 4.71 4.71 4.80 4.83 4.92 v v v ppor1r v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0] = 01b porlev[1:0] = 10b ?4.39 4.55 ?v v table 35. dc programming specifications symbol description min typ max units notes i ddp supply current during programming or verify ? 15 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.21 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify 3.5 ? vdd v flash enpb flash endurance (per block) [14] 100 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [14,15] 25,600 ? ? ? erase/write cycles. flash dr flash data retention [16] 15 ? ? years notes 14. for the full temperature range, the user must employ a temperat ure sensor user module (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 15. a maximum of 256 x 100 block endurance cycles is allowed. 16. flash data retention based on the use condition of 7000 hours at t a 105c and the remaining time at t a 65c. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 38 of 53 ac electrical characteristics ac chip level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 36. ac chip level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.04 24 24.96 mhz trimmed. utilizing factory trim values. f imo6 internal main oscillator frequency for 6mhz 5.5 6 6.5 [17] mhz trimmed for 5v or 3.3v operation using factory trim values. slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.90 12 12.48 mhz f blk5 digital psoc block frequency ? ? ? mhz 4.75v< vdd <5.25v f blk33 digital psoc block frequency 0 24 24.96 [17] mhz 3.0v cy8c28xxx document number: 001-46339 rev. *f page 39 of 53 figure 8. pll lock timing diagram figure 9. pll lock for low gain setting timing diagram figure 10. external crystal oscillator startup timing diagram figure 11. 24 mhz period jitter (imo) timing diagram figure 12. 32 khz period jitter (eco) timing diagram 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os jitter24m1 f 24m jitter32k f 32k2 [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 40 of 53 ac general purpose i/o specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. figure 13. gpio timing diagram ac operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. the operational amplifiers covered by these specifications are components of both the analog continuous time psoc blocks and the analog switched cap psoc blocks. settling times, slew rates, and gain bandwidth ar e based on the analog continuous time psoc block. table 37. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.48 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 22 ns vdd = 4.75 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 22 ns vdd = 4.75 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 9 27 ? ns vdd = 4.75 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 9 22 ? ns vdd = 4.75 to 5.25v, 10% - 90% table 38. ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s (active probe loading, unity gain) t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s (active probe loading, unity gain) sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s (active probe loading, unity gain) sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s (active probe loading, unity gain) tfallf tfalls tris ef trises 90% 10% gpio pin output voltage [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 41 of 53 when bypassed by a capacitor on p2[4], the noise of the analog gr ound signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacit or. figure 14. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 15. typical opamp noise bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz power = medium, opamp bias = high ?100?nv/rt-hz table 38. ac operational amplifier specifications (continued) symbol description min typ max units notes vnagnd eme ra ld = 2*vbg -150 -140 -130 -120 -110 -100 -90 0.001 0.01 0.1 1 10 100 e0 . 0 e0 . 0 1 e0 . 1 e1 . 0 e1 0 . 0 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 42 of 53 ac type-e operational amplifier specifications the following table lists the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. the operational amplifiers covered by these specifications are components of the limited type e analog psoc blocks. ac low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. ac analog mux bus specifications the following table lists the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. ac digital block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 39. ac type-e operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time ? 75 100 ns 50 mv overdrive table 40. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 41. ac analog mux bus specifications symbol description min typ max units notes f sw switch rate ? ? 3.17 mhz table 42. ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency 24.96 timer capture pulse width 50 [18] ? ? ns maximum frequency, no capture ? ? 24.96 mhz 4.75v < vdd < 5.25v. maximum frequency, with capture ? ? 24.96 mhz counter enable pulse width 50 [18] ? ? ns maximum frequency, no enable input ? ? 24.96 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.96 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [18] ? ? ns disable mode 50 [18] ? ? ns maximum frequency ? ? 24.96 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 24.96 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.96 mhz spim maximum input clock frequency ? ? 4.16 mhz maximum data rate at 2.08 mhz due to 2 x over clocking. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 43 of 53 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. ac sar10 adc specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. spis maximum input clock frequency ? ? 2.08 mhz width of ss_ negated between transmissions 50 [18] ? ? ns trans- mitter maximum input clock frequency ? ? 8.32 mhz maximum data rate at 1.04 mhz due to 8 x over clocking. receiver maximum input clock frequency ? 16 24.96 mhz maximum data rate at 3.12 mhz due to 8 x over clocking. all functions maximum block clocking frequency (> 4.75v) 24.96 4.75v < vdd < 5.25v. table 42. ac digital block specifications (continued) function description min typ max units notes note 18. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). table 43. ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 3 3 s s t sob falling settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 3 3 s s sr rob rising slew rate (20% to 80%), 1v step, 100 pf load power = low power = high 0.6 0.6 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100 pf load power = low power = high 0.6 0.6 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 44. ac sar10 adc specifications symbol description min typ max units notes f insar10 input clock frequency for sar10 adc ? ? 2.0 mhz f ssar10 sample rate for sar10 adc sar10 adc resolution = 10 bits ? ? 142.9 ksps for 10-bit resolution, the sample rate is the adc's input clock divided by 14. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 44 of 53 ac external clock specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. ac programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. ac i 2 c specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 105 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 45. ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 46. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 40 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 55 ns t rsclk rise time of sclk 1 ? 70 ns t eraseall flash erase time (bulk) ? 80 ? ms erase all blocks and protection fields at once. t program_hot flash block erase + flash block write time ? ? 100 [14] ms 0c tj 100c t program_cold flash block erase + flash block write time ? ? 200 [14] ms -40c tj 0c table 47. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 45 of 53 figure 16. definition for timing for fast/standard mode on the i 2 c bus t sudati2c data setup time 250 ?100 [19] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns table 47. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max note 19. a fast-mode i2c-bus device can be used in a stan dard-mode i2c-bus system, but the requirement t su;dat ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 46 of 53 packaging information this section illustrates the packaging spec ifications for the cy8c28xxx psoc devices , along with the thermal impedances for eac h package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensio ns, refer to drawings at http://www.cypress.com/design/mr10161 . packaging dimensions figure 17. 20-pin (210-mil) ssop 51-85077 *c [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 47 of 53 figure 18. 28-pin (210-mil) ssop figure 19. 44-pin tqfp 51-85079*c 51-85064 *c [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 48 of 53 thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 48. thermal impedances per package package typical ja [20] 20 ssop 80.8 c/w 28 ssop 45.4 c/w 44 tqfp 24.0 c/w table 49. typical package capacitance on crystal pins package package capacitance 20 ssop pin9 = 0.0056 pf pin11 = 0.006048 pf 28 ssop pin13 = 0.006796 pf pin15 = 0.006755 pf 44 tqfp pin16 = 0.009428 pf pin18 = 0.008635 pf table 50. solder reflow peak temperature package minimum peak temperature [21] maximum peak temperature 20 ssop 245 c 260 c 28 ssop 245 c 260 c 44 tqfp 245 c 260 c notes 20. t j = t a + power x ja 21. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 49 of 53 development tool selection this section presents the development tools available for all current psoc device families including the cy8c28xxx family. software psoc designer at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for over half a decade. psoc designer is available free of charge at http://www.cypre ss.com/psocdesigner . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory prog ramming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com/psocprogrammer. psoc c compilers cy3202 is the optional upgrade to psoc designer that enables the imagecraft c compiler. it can be purchased from the cypress online store. at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click psoc (programmable system-on-chip) to view a current list of available items. development kits all development kits can be purchased from the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specif ic memory locations. advanced emulation features are suppor ted in psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator pod kit for cy8c29x66 psoc family cat-5 adapter mini-eval programming board 110 ~ 240v power supply, euro-plug adapter issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples cy3210-expressdk psoc express development kit the cy3210-expressdk is for ad vanced prototyping and devel- opment with psoc express (may be used with ice-cube in-circuit emulator). it provides access to i 2 c buses, voltage reference, switches, upgradeable modules and more. the kit includes: psoc express software cd express development board 4 fan modules 2 proto modules miniprog in-system serial programmer minieval pcb evaluation board jumper wire kit usb 2.0 cable serial cable (db9) 110 ~ 240v power supply, euro-plug adapter 2 cy8c24423a-24pxi 28-pdip chip samples 2 cy8c27443-24pxi 28-pdip chip samples 2 cy8c29466-24pxi 28-pdip chip samples evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping prog rammer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 50 of 53 cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable device programmers all device programmers can be purchased from the cypress online store. cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note : the cy3207issp programmer needs the psoc issp software. it is not compatible with the psoc programmer software. the latest psoc issp software for this kit can be downloaded from http://www.cypress.com . the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable accessories (emulation and programming) 3rd-party tools several tools have been specially designed by the following 3rd-party vendors to accompany psoc devices during devel- opment and production. specific details for each of these tools can be found at http://www.cypress.com under design resources >> evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, see application note ?debugging - build a psoc emulator into your board - an2323? at http://www.cypress.com/an2323. table 51. emulation and programming accessories part # pin package pod kit [22] foot kit [23] adapter [24] cy8c28243-12pvxq 20ssop cy3250-28xxx cy3250-20ssop-fk adapters can be found at http://www.emulation.com. cy8c28413-12pvxq cy8c28433-12pvxq cy8c28445-12pvxq cy8c28452-12pvxq 28 ssop cy3250-28xxx cy3250-28ssop-fk cy8c28513-12axq CY8C28533-12AXQ cy8c28545-12axq 44 tqfp cy3250-28xxx cy3250-44tqfp-fk notes 22. pod kit contains an emulation pod, a flex-cable (connects the pod to the ice), two feet, and device samples. 23. foot kit includes surface mount feet that can be soldered to the target pcb. 24. programming adapter converts non-dip pack age to dip footprint. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com . [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 51 of 53 ordering information the following tabl e lists the cy8c28xxx psoc devices key package features and ordering codes . note for die sales information, contact a local cypress s ales office or field applications engineer (fae). package ordering code temperature range capsense digital blocks regular analog blocks limited analog blocks hw i 2 c decimators 10-bit sar adc digital i/o pins analog inputs analog outputs flash (kbytes) ram (kbytes) xres pin 28-pin (210 mil) ssop cy8c28403-12pvxq -40 to 85 n 12 0 0 2 0 y 24 8 0 16 1 y 28-pin (210 mil) ssop (tape and reel) cy8c28403-12pvxqt -40 to 85 n 12 0 0 2 0 y 24 8 0 16 1 y 28-pin (210 mil) ssop cy 8c28413-12pvxq -40 to 105 y 12 0 4 1 2 y 24 24 0 16 1 y 28-pin (210 mil) ssop (tape and reel) cy8c28413-12pvxqt -40 to 105 y 12 0 4 1 2 y 24 24 0 16 1 y 44-pin tqfp cy8c28513-12axq -40 to 105 y 12 0 4 1 2 y 40 40 0 16 1 y 44-pin tqfp (tape and reel) cy8c28513-12axqt -40 to 105 y 12 0 4 1 2 y 40 40 0 16 1 y 28-pin (210 mil) ssop cy 8c28433-12pvxq -40 to 105 y 12 6 4 1 4 y 24 24 2 16 1 y 28-pin (210 mil) ssop (tape and reel) cy8c28433-12pvxqt -40 to 105 y 12 6 4 1 4 y 24 24 2 16 1 y 44-pin tqfp CY8C28533-12AXQ -40 to 105 y 12 6 4 1 4 y 40 40 2 16 1 y 44-pin tqfp (tape and reel) CY8C28533-12AXQt -40 to 105 y 12 6 4 1 4 y 40 40 2 16 1 y 20-pin (210 mil) ssop cy 8c28243-12pvxq -40 to 105 n 12 12 0 2 4 y 16 16 4 16 1 y 20-pin (210 mil) ssop (tape and reel) cy8c28243-12pvxqt -40 to 105 n 12 12 0 2 4 y 16 16 4 16 1 y 28-pin (210 mil) ssop cy 8c28445-12pvxq -40 to 105 y 12 12 4 2 4 y 24 24 4 16 1 y 28-pin (210 mil) ssop (tape and reel) cy8c28445-12pvxqt -40 to 105 y 12 12 4 2 4 y 24 24 4 16 1 y 44-pin tqfp cy8c28545-12axq -40 to 105 y 12 12 4 2 4 y 40 40 4 16 1 y 44-pin tqfp (tape and reel) cy8c28545-12axqt -40 to 105 y 12 12 4 2 4 y 40 40 4 16 1 y 28-pin (210 mil) ssop cy 8c28452-12pvxq -40 to 105 y 8 12 4 1 4 n 24 24 4 16 1 y 28-pin (210 mil) ssop (tape and reel) cy8c28452-12pvxqt -40 to 105 y 8 12 4 1 4 n 24 24 4 16 1 y [+] feedback
cy8c28xxx document number: 001-46339 rev. *f page 52 of 53 ordering code definitions cy 8 c 28 xxx - sp xxxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended ltx/lfx/lkx = qfn pb-free ax = tqfp pb-free speed: 12 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress [+] feedback
document number: 001-46339 rev. *f revised november 10, 2009 page 53 of 53 psoc designer? and programmable system-on-chip? are trademarks and psoc? is a registered trademark of cypress semiconductor cor p. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublicensed associate d companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by phi lips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c28xxx ? cypress semiconductor corporation, 2008-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cente rs, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at www.cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document title: cy8c28243, cy8c28403, cy8c28413, cy 8c28433, cy8c28445, cy8c28452 , cy8c28513, cy8c28533, cy8c28545, extended industrial psoc? programmable system-on-chip document number: 001-46339 revision ecn no. origin of change submission date description of change ** 2505101 kiy/hmi/aesa 06/26/2008 new document (revision **). *a 2593460 btk/pyrs 10/20/2008 converted from advance to preliminary changed part numbers and title extensive updates to content *b 2652217 btk/pyrs 02/02/09 extensive updates to content. added registers maps. updated getting started section updated development tools section added some sar10 adc specifications. added more analog system figures. *c 2675937 btk 03/18/09 updated dc analog reference specifications changed temperature grade ratings in part numbers from e to q minor content updates *d 2679015 hmi 03/26/2009 post to external web. *e 2750217 tdu 08/10/09 updates to electrical specificatons section minor content updates *f 2805324 alh 11/11/09 added contents page. updated electrical specifications . [+] feedback

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